Semiconductor devices, and methods of manufacture of the same

ABSTRACT

The semiconductor laser device has the lower clad layer, active layer, upper clad layer, contact layer, the insulating film, and the positive electrode sequentially formed on the semiconductor substrate. The upper clad layer, the contact layer and the insulating film form the ridge. The positive electrode covers the upper and side faces of the ridge. The thickness of the positive electrode on the upper and side faces of the ridge is preferably substantially the same and it is not less than 150 nm.

FIELD OF THE INVENTION

[0001] The present invention relates to semiconductor devices having aridge structure, such as the ridge-type semiconductor laser devices. Theridge structure may be formed on top of a surface of a substrate, orwithin a surface of a substrate, as in the case of double channelsemiconductor devices, such as Double Channel Planar BuriedHeterostructures.

BACKGROUND OF THE INVENTION

[0002] Conventionally, semiconductor devices having desired electriccircuitry or desired electric elements have been formed by forming amulti-layer film structure on a semiconductor substrate and thenperforming etching or the like.

[0003]FIG. 5 is a sectional view of a conventional semiconductor laserdevice which is an example of a semiconductor device. This semiconductorlaser device has the ridge 12′ in a stripe shape, and light and electriccurrent are confined by this ridge 12′. As a result, this semiconductorlaser device exhibits good lasing ability with a simple structure, andis used in various fields such as optical communication, opticalrecording and measurements, for light-emitting devices and optical fiberamplifier excitation apparatus.

[0004] This semiconductor laser device has the lower clad layer 3,active layer 4, upper clad layer 5, contact layer 9 and insulating film6 sequentially formed on the upper face of semiconductor substrate 2.Apart of the upper clad layer 5, contact layer 9 and the insulating film6 together form ridge 12′. Moreover, the negative electrode 1 is formedon the lower face of the semiconductor substrate 2, and the positiveelectrode 17 is formed on the upper face of the semiconductor laserdevice.

[0005] This conventional semiconductor laser device is manufactured witha method that is shown in FIGS. 6A to 6C and FIGS. 7A to 7C. As shown inFIG. 6A, the lower clad layer 3, active layer 4, upper clad layer 5 andthe contact layer 9 are sequentially formed on one surface of thesemiconductor substrate 2. Then, the resist 10 is applied to form a filmon the contact layer 9.

[0006] Thereafter, as shown in FIG. 6B, the contact layer 9 and theupper clad layer 5 are etched by to thereby form the ridge 12′ havingthe same width as that of the resist 10. Subsequently, as shown in FIG.6C, the resist 10 is removed, and the insulating film 6 is formed on theexposed surfaces of the upper clad layer 5 and the contact layer 9.Thus, the insulating film 6 completely covers the ridge 12′.

[0007] Subsequently, as shown in FIG. 7A, the resist 11 is applied onthe insulating film 6. This resist 11 is applied in such a manner thatit covers the ridge 12′. Although not shown in the drawing, anotherresist is formed above the resist 11 thereby making the surface abovethe ridge 12′ and its periphery flat. Thereafter, as shown in FIG. 7B,photo-lithography and oxygen plasma ashing processing are performedthereto, to remove the resist 11 on the upper face of the ridge 12′ andthe peripheral portion thereof, up to the height of the insulating film6 of the ridge 12′, to thereby expose the insulating film 6 on the upperface of the ridge 12′.

[0008] Subsequently, as shown in FIG. 7C, the insulating film 6 on theupper face of the ridge 12′ is removed by plasma etching processing, tothereby expose the contact layer 9. Then, the resist 11 is completelyremoved, and the positive electrode 17 (see FIG. 5) is deposited on theentire upper face including the side of the ridge 12′. Next, thethickness of the substrate is reduced by milling and polishing the lowerface of the substrate. Finally, the negative electrode 1 (see FIG. 5) isdeposited on the lower face of the semiconductor substrate 2. Thus, theconventional ridge-type semiconductor laser device is obtained.

[0009] The positive electrode 17 is typically formed using severalphoto-lithographic steps, a dry deposition step, and a plating step.Specifically, a first photo-lithographic step is used to form a lift-offmask which does not cover the area where electrode 17 is to be formed.This step typically includes the step of using an ionic developersolution (e.g., alkaline solutions such NaOH, KOH, andtetra-methylammonium hydroxide, TMAH) to develop a pattern in thelift-off mask. Next, a dry deposition process (e.g., sputtering) is usedto deposit a thin metallic adhesion layer, followed by a thin metallicbarrier layer which resists the diffusion of gold into the adhesionlayer. The portions of the metal layer that are formed on the lift-offmask, which are not wanted in the finished device, are removed by asecond photo-lithographic step which removes the underlying lift-offmask by exposing it to an organic solvent (e.g., washing it in thesolvent).

[0010] Next, a thin gold seed layer for a subsequent electroplating stepis usually deposited over the surface of the wafer. However, this stepcan be omitted if gold can be directly electroplated onto the barrierlayer. A third photo-lithographic step is then used to form a patternedplating mask over the surface of the substrate such that the top ofelectrode 17 is exposed. This photo-lithographic step includes the useof an ionic developer solution to develop a pattern in the plating masklayer. Next, a thick layer of gold is typically plated over the top ofelectrode 17 using an ionic plating solution and the plating mask. Thenthe plating mask is removed by washing in an organic solvent (a fourthphoto-lithographic step). If desired, a brief exposure to a gold etchantcan be used to remove the seed layer which was previously covered by theplating mask.

[0011] Similar steps are used to form the negative electrode 1,including exposure to one or more ionic developer solutions and one ormore organic solvents. The milling process used to thin the substratealso uses organic solvents, and may sometimes use ionic developersolutions.

[0012] In the conventional semiconductor laser device, however, when thepositive electrode 17 and the negative electrode 1 are formed using thephoto-lithography and plating steps described above, there often occursan erosion of the contact layer 9. When the contact layer 9 is eroded,the current channel of the obtained semiconductor laser device becomesnarrow and thereby the electric resistance increases. As a result, thereis a drawback that the optical output of the semiconductor laser devicedecreases. If the erosion is severe, most of the contact layer 9 and theupper clad layer 5 are affected, thereby the optical output furtherdecreases.

[0013] As part of making their invention, the inventors have found thatthe plasma etching process shown in FIG. 7C causes the top edges ofinsulating film 6 to have inclined surfaces 23 instead of flat surfaces,as shown in FIG. 8, and as shown in an enlarged view in FIG. 11. Theinclined surfaces 23 create small gaps 24 between insulating film 6 andcontact layer 9 of the ridge, which create discontinuities in thesurface over which electrode layer 17 is deposited. With experiments onseveral samples conducted as part of making their invention, theinventors have further found that an erosion 22 is observed near theupper portion of the contact layer 9 near these small gaps 24. They havealso found that a crack 21 extending all the way through the electrodelayer 17 is generally observed near the erosion 22 at the boundarybetween the positive electrode 17 and the insulating film 6. This isshown at the left side of the device in FIG. 8. We have shown on theright side of the device of FIG. 8 the case where the crack does notextend all the way through the electrode layer. Although FIG. 8 showsthe erosion 22 only on the left side of the semiconductor laser device,similar erosion is observed on the right side as well.

[0014] Moreover, as part of making their invention, the inventors havefound that the ionic solutions used during the photo-lithography andplating steps infiltrates to the contact layer 9 via the crack 21 anderodes the contact layer 9 due to electrochemical reaction.

[0015] The present invention is focused on reducing, and preferablyeliminating, this undesirable erosion.

SUMMARY OF THE INVENTION

[0016] It is an object of the present invention to provide semiconductordevices which do not have cracks in their positive electrodes or erosionof their contact layers. It is another object of this invention toprovide methods by which such semiconductor devices can be manufacturedeasily and efficiently.

[0017] A first invention of the present application provides a novelshaped ridge structure which substantially reduces, and in most caseseliminates, the small gaps between the insulating film and the ridgewhich cause the above-described discontinuities. An exemplary ridgeaccording to this invention comprises at least one layer of asemiconductor material, and has a base attached to a surface of asubstrate, an upper face located above the base, a first body sectionlocated between the base and the upper face, a second body sectionlocated between the first body section and the upper face, and at leastone side face located between the ridge's upper face and the base and toone side of the first and second body sections. The side face has afirst area which spans over the first body section and a second areawhich spans over the second body section. The side face further has astraight mesa slope or a forward mesa slope in the first area and areverse mesa slope in the second area. The exemplary ridge furthercomprises a dielectric layer disposed on the first side face andcovering the first area, the second area, and preferably the upper faceof the ridge prior to the application of the plasma etching step. Afterthe plasma etching process, the portion of the dielectric layer coveringthe upper face is substantially removed, and a portion of the dielectriclayer which covers the second area near the upper surface issubstantially removed in a manner that provides a relatively smoothsurface. In a preferred embodiment, the material of the ridge is moreresistant to plasma etching than the material of the dielectric layer.

[0018] A second invention of the present application may be used withthe first invention of the present application or separate therefrom. Anexemplary ridge according to this invention comprises at least one layerof a semiconductor material, and has a base attached to a surface of asubstrate, an upper face located above the base, and at least one sideface located between the ridge's upper face and the base. The exemplaryridge further comprises a conductive layer disposed on at least aportion of the ridge such that the conductive layer covers the at leastone side face of the ridge with a first thickness (T₁) at the ridgeportion, and further covers the ridge's upper face with a secondthickness (T₂) at the ridge portion. The first thickness of conductivematerial on the side face is significantly thicker than that used inconventional devices, being equal to or greater than 150 nm, and/orequal to or greater than fifty percent of the second thickness. Thelarger thickness can be achieved in a dry deposition process by tiltingthe ridge and its supporting substrate with respect to the flowdirection of deposition material and by rotating the substrate around asurface normal of the substrate during the dry deposition process. Thegreater than normal thickness of conductive material on the ridge's sideface resists the occurrence of cracks in the conductive material.

[0019] Other objects and features of this invention will become apparentfrom the following description with reference to the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020]FIG. 1 is a sectional view of a semiconductor laser device, beingone embodiment of the first and second inventions of the presentapplication;

[0021]FIG. 2A to FIG. 2C are sectional views showing the manufacturingprocess of the semiconductor laser device shown in FIG. 1 according tothe first invention of the present application;

[0022]FIG. 3A to FIG. 3C are sectional views showing continuation of themanufacturing process of the semiconductor laser device shown in FIG. 1according to the first invention of the present application;

[0023] FIGS. 4A-4B are enlarged sectional views of a ridge portion ofthe semiconductor laser device under selected stages of manufactureaccording to the first invention of the present application;

[0024]FIG. 4C is an enlarged sectional view of the ridge portion of thesemiconductor laser device after completion of manufacture according toboth the first and second inventions of the present application;

[0025]FIG. 5 is a sectional view of a semiconductor laser device whichis an example of a conventional semiconductor device according to theprior art;

[0026]FIG. 6A to FIG. 6C are sectional views showing the manufacturingprocess of the semiconductor laser device shown in FIG. 5 according tothe prior art;

[0027]FIG. 7A to FIG. 7C are sectional views showing continuation of themanufacturing process of the semiconductor laser device shown in FIG. 5according to the prior art;

[0028]FIG. 8 is a sectional view showing erosion of the contact layerand crack in the positive electrode of the conventional semiconductorlaser device according to the prior art;

[0029]FIG. 9 is a sectional view showing erosion of the contact layerand crack in the positive electrode of a semiconductor laser accordingto the first invention of the present application which can benefit fromthe second invention according to the present application;

[0030]FIG. 10 is a partial sectional view of a ridge of a conventionalsemiconductor device after a plasma ashing step according to the priorart;

[0031]FIG. 11 is a partial sectional view of a ridge of a conventionalsemiconductor device after a plasma etching step according to the priorart;

[0032]FIG. 12 is a partial sectional view of a ridge of an exemplarysemiconductor device after a plasma ashing step according to the presentinvention;

[0033]FIG. 13 is a partial sectional view of the ridge of the exemplarysemiconductor device previously shown in FIG. 12 after a plasma etchingstep according to the present invention;

[0034]FIG. 14 is a partial sectional view of the ridge of the exemplarysemiconductor device shown in FIG. 13 after the deposition of theelectrode layer according to the present invention; and

[0035]FIG. 15 is a sectional view of an exemplary ridge according to thepresent inventions.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] An exemplary semiconductor device which incorporates bothinventions of the present application, and exemplary methods thereof,are described below with reference to the accompanying drawings.

[0037]FIG. 1 is a general sectional view of the semiconductor laserdevice according to one embodiment of the present inventions, and FIG.4C is an enlarged view of the ridge section 12 thereof. Referring toFIG. 1, a multi-layer film substrate 31 forming this semiconductor laserdevice has a lower clad layer 3, an active layer 4, an upper clad layer5, a contact layer 9, and an insulating film 6 (i.e., insulating layer)formed on one surface of the semiconductor substrate 2. The upper cladlayer 5, the contact layer 9 and the insulating film 6 together form aridge 12. In addition, a negative electrode 1 is formed on the othersurface of the semiconductor substrate 2, and a positive electrode 7 isformed above the multi-layer film substrate 31.

[0038] This semiconductor laser device is manufactured with a processthat will be explained with reference to FIG. 2A to FIG. 2C, FIG. 3A toFIG. 3C, and FIG. 4A to FIG. 4C. As shown in FIG. 2A, the lower cladlayer 3 having a composition of n-type AlGaAs, the active layer 4, theupper clad layer 5 having a composition of p-type AlGaAs, and thecontact layer 9 preferably having a composition of p-type GaAs, aresequentially formed on the top surface of the semiconductor substrate 2having a composition of n-type GaAs. The various layers may be formedusing the thin-film epitaxial growth method such as the MOCVD or MBEmethod. A resist 10 is then applied to form a film on the contact layer9.

[0039] Thereafter, as shown in FIG. 2B, the contact layer 9 and theupper clad layer 5 are etched by wet etching processing using citricacid type solution to thereby form the ridge 12 having the same width asthat of the resist 10.

[0040] Subsequently, the resist 10 on the upper face of the multi-layerfilm substrate 31 is removed by dissolving it using a stripping solutionand the resist 10 is then completely removed by the oxygen plasma ashingprocessing. FIG. 4A shows an enlarged cross-sectional view of the ridgeafter the completion of these steps. As indicated in FIG. 4A, the ridgehas a base attached to the substrate, an upper face located above thebase, and side faces located between the ridge's upper face and thebase. As can be seen in the figure, the side faces essentially have an“hourglass” shape which divides the body of the ridge into two majorsections: a lower body section 41 and an upper body section 42. The sidefaces at the lower body section 41 have “forward mesa” slopes, meaningthat one moves forward as one climbs up the side face from the bottom ofthe ridge. A more precise definition of “forward mesa slope” is that theupper end of the sloped face is closer to the central line 43 of theridge than the lower end of the sloped face. The side faces at the upperbody section 42 have “reverse mesa” slopes, meaning that one movesbackwards (in the reverse direction) as one climbs up the sloped sideface. A more precise definition of “reverse mesa slope” is that theupper end of the sloped face is further away from the center line 43 ofthe ridge than the lower end of the sloped face. The upper edges of theridge (i.e., the upper edges of body section 42) are rounded over by thestep of removing resist layer 10 by stripping and oxygen plasma ashingprocessing, and thus portions 9A of contact layer 9 are removed. Theslopes of the side faces at removed portions 9A may be straight or“forward mesa” sloped. In this case, second body section 42 does notextend all the way to the upper face of the ridge.

[0041] The hourglass shaped ridge is achieved with citric acid etchingsolution acting on the following composition of ridge 12: contact layer9 composed of p-type GaAs, and having a thickness of 400 nm; upper cladlayer 5 composed of p-type Al_(0.3)Ga_(0.7)As and having a thickness of1400 nm (1.4 μm) to 1500 nm (1.5 μm). With a citric acid etchingsolution and this selection of materials, there is a difference betweenthe etching speed of the contact layer 9 and the etching speed of theupper clad layer 5 which creates the forward mesa slope at the lowerbody section 41 and a reverse mesa slope at the upper body section 42.Thus, the first invention of this application is applied to thisexemplary semiconductor device.

[0042] As the next step in the exemplary manufacturing method, theinsulating film 6 is formed on the upper face of the multi-layer filmsubstrate 31, using the plasma CVD method or the like. This insulatingfilm 6 is formed on the upper face of the upper clad layer 5, on theupper face of the ridge 12 and on the side of the ridge 12. Theinsulating film 6 may be a silicon nitride film, and has a thickness ofapproximately 120 nm in this example. The result of this step is showngenerally in FIG. 2C, and in an expanded view in FIG. 4B.

[0043] Subsequently, as shown in FIG. 3A, the resist 11 is formed abovethe ridge 12 in such a manner that the resists rises above the ridge 12in height. A spin coat process or the like is used for application ofthe resist 11.

[0044] Subsequently, as shown in FIG. 3B, a portion of the resist 11 isremoved by the photo-lithography and oxygen plasma etching processing.The etching processing is controlled in such a manner that the etchingstops when the insulating film 6 above the ridge 12 gets exposed.

[0045] Thereafter, for example, as shown in FIG. 3C, FREON-gas plasmaetching processing is performed to remove the insulating film 6 on theupper face of the ridge 12. The etching process is controlled in such amanner that the etching stops when the contact layer 9 is exposed, witha small amount of over-etching. The thickness of the resist 11 at thisstage is from 1.6 μm to 1.8 μm, as measured from the top of layer 6 (inthe area away from the ridge), and is from 1.8 μm to 2 μm, as measuredfrom the top of layer 5 (in the area away from the ridge). Therefore,the resist 11 substantially serves as a protective cover for theportions of the insulating film 6 which are not to be removed, whenetching the insulating film 6 on the upper face of the ridge 12.However, a small portion of layer 6 is removed from the top of the sidefaces of the ridge, generally approximately 100 nm down from the upperface of the ridge (looking ahead to FIG. 4C, it can be seen that the topof layer 6 on the side face is somewhat below the top of the ridge'supper face). As will be described in greater detail below, the etchingof layer 6 with the reverse mesa slope at the upper end of the ridgeprovides the advantageous effect of allowing a significant amount ofover-etching without creating large discontinuities in the surface ofthe side face, as can be the case in the prior art.

[0046] The resist 11 is then dissolved and removed using a strippingsolution (e.g., organic solvent), and the oxygen plasma ashingprocessing is applied to thereby remove the remaining resist 11. As thestripping solution, one containing aromatic hydrocarbon, phenol andalkyl benzene sulfonate at a ratio of 6:2:2 may be used.

[0047] Next, the positive electrode 7 (see FIG. 1) having a thickness of200 nm is formed on the exposed face of the contact layer 9 and on theinsulating film 6, using the photo-lithography lift-off technique and adry deposition process, such as metal evaporation, metal sputtering(e.g., collimated sputtering), etc. In the lift-off technique, aphotoresist layer (usually having a thickness of 2 microns or more) isformed over the top surface of the substrate, and then patterned toremove photoresist material in those locations where the positiveelectrode 7 is to be formed. In this example, the photoresist materialis removed over the top and side faces of the ridge. The conductivematerial for electrode 7 is then deposited over the entire top surfaceof the substrate, including the top surfaces of the patternedphotoresist layer and the top and side faces of the ridge, preferablywith a dry deposition process. Unwanted metal is deposited over thephotoresist layer. The photoresist is subsequently removed with astripping solvent, which lifts the unwanted metal away from thesubstrate, leaving behind the desired metal pattern. The strippingsolution is generally an organic solvent. The deposited conductive layerfor electrode 7 generally comprises a first sublayer of an adhesivemetal (such as titanium—Ti) with a thickness of at least 75 nm, and asecond sublayer of a gold-diffusion barrier layer (such at platinum—Pt)with a thickness of at least 75 nm. As described below in greaterdetail, a thick gold layer will be subsequently formed over electrode 7by electroplating, and the barrier sub-layer prevent gold interactingwith the adhesion sub-layer. In preferred embodiments, both the adhesionsublayer and the barrier sublayer preferably comprise substantially nogold (Au), each comprising not more than 5% of gold by weight, andpreferably not more than 0.5% by weight. The dry deposition processpreferably provides each sub-layer with a lustrous surface morphology,as opposed to the non-lustrous surface morphology obtained withconventional plating processes used in the electronics industry.

[0048] The dry deposition process may be performed by a vapor depositionapparatus or a sputtering apparatus (such as with a collimator), or thelike, all of which are generically referred to as dry depositionapparatuses herein. The dry deposition apparatus comprises a depositionaxis along which deposition material flows in low pressure gaseousenvironment (e.g., near vacuum), and a holder for holding a substratewithin the deposition field of the apparatus. The holder is capable ofrevolving about a center axis of the holder, this center axis beingsubstantially parallel to a normal vector of the top surface of thesubstrate which is held by the holder. The holder is oriented withindeposition field such that its center axis is inclined with respect tothe deposition axis (i.e., the center axis and the deposition axis forma non-zero acute angle.) This configuration enables the thickness of theelectrode on the upper face and the thickness on the side face of theridge 12 to be made substantially the same. Accordingly, the multi-layerfilm substrate 31 with ridge 12 is placed within the holder, and theholder is set with its center line at an incline, and is rotated withinthe deposition field during the deposition process. As a result,electrode material is adhered to the upper and side faces of the ridge12 and the lower surfaces of layer 6, to form the positive electrode 7.In this manner, electrode 7 is formed to a thickness of at least 150 nm,and more preferably of at least 200 nm, without being exposed to anionic solution (e.g., developer, plating solution), an organic solvent,or other liquid.

[0049] Next, the positive electrode 7 is then plated with a thick layerof gold (Au), such as by using the steps previously described for theprior art device. Those steps including using an aqueous ionic developersolution to define a pattern in the plating mask, and using an aqueousionic plating solution to plate gold material. Each of these ionicsolutions contacts the metal electrode 7, and has the potential oferoding portions of the ridge if they infiltrate through the electrode7. However, the thickness of electrode 7 on the side faces of the ridgeas taught by the present invention substantially prevents the occurrenceof the infiltration and the occurrence of the erosion.

[0050] Gold is a more ductile material and softer material than thematerials used for the sublayers of electrode 7. (Stated the other way,the materials used for the sublayers of electrode 7 are less ductile andharder than gold). In bulk crystalline form, gold has a hardness ofapproximately 25 on the Vicker's scale, platinum has a hardness ofapproximately 40, and titanium has a hardness of approximately 60.Values for these materials in the form of deposited films will varysomewhat from the values in bulk crystalline form, but the relativeordering of the values is substantially the same. In preferredembodiments, the sublayers of electrode 7 which provide the first 150 nmof the electrode's thickness on the side face (as measured from theinterface with the ridge) are preferably comprised of materials havinghardness values of 30 or more on the Vicker's scale (and as measured intheir bulk crystalline form), and 60 or less on the Vicker's scale.

[0051] Next, the lower face of the semiconductor substrate 2 is milledand polished, and then the negative electrode 1 is formed thereon.Similar steps are used to form the negative electrode 1, includingexposure to one or more ionic developer solutions and one or moreorganic solvents. The milling process used to thin the substrate alsouses organic solvents, and may sometimes use ionic developer solutions.

[0052] The result of these steps is shown generally in FIG. 1, and in anexpanded cross-sectional view in FIG. 4C.

[0053] The multi-layer film substrate 31 formed by the above-describedprocess is cleaved, assembled as a module, and mounted to therebycomplete the semiconductor laser device.

[0054] Thus, according to one aspect of the second invention of thepresent application, the positive electrode 7 has substantially the samethickness on the upper face and on the side face of the ridge 12 (bysubstantially the same thickness, we mean that the two thicknesses arewithin 10% of one another). In this particular example, a 200 nm thickpositive electrode 7 is formed on the side faces and the upper face ofthe ridge 12. The inventors have generally found that a thickness of 150nm or more for electrode layer 7 on the side face (denoted as thicknessT₁ in FIG. 4C) is sufficient for preventing the formation of cracks inelectrode 7 at the boundary between electrode 7 and insulating layer 6,and for preventing the erosion of the contact layer 9. FIG. 9 shows acase where the thickness T₁ is significantly below this value, and wherethe formation of crack 21 and erosion of area 22 have occurred. As aspecial note to the exemplary ridge 12 shown in FIG. 9, the reverse mesaform of the upper section 42 of ridge 12 causes mechanical stress to beconcentrated on this upper section, which in turn causes a distortion onthe positive electrode 17 on the side of the ridge 12, to thereby causethe crack 21. The use of a value of 150 nm or more for thickness T₁effectively counters this stress and distortion.

[0055] Further Advantages of the Ridge with a Reverse Mesa Top Section

[0056] As stated above, the novel shaped ridge structure shown in FIGS.4A-4C is advantageous in reducing, and in most cases eliminating, thesmall gaps 24 shown in FIGS. 8 and 11 which cause discontinuities in thesurface of electrode layer 7. There are further advantages related toover etching in the plasma etching processes shown in FIGS. 7C and 3C.

[0057] As is known in the art, the deposited thickness of resist 11 anddielectric layer 6 shown in FIG. 7A can vary to a significant degreeover the surface of the wafer. As is common to the art, over etchingduring the plasma ashing and plasma etching steps shown in FIGS. 3B,7Band 3C,7C is often performed to account for such variations. In otherwords, the duration of the etching process is selected so that thethickest portions of these layers are completely etched, with anadditional margin of time added as a safety margin. As a result, thoseareas where the layers are the thinnest are over etched to a largedegree.

[0058] The novel shaped ridge structure of the first invention providesan additional advantage of being more resistant to over etching than theprior art forward mesa ridge. To illustrate this point, the prior artforward mesa ridge is shown in FIG. 10 after the plasma ashing step hasbeen performed. An over etching distance OE1, as measured from the topof the ridge to the lowest point of resist layer 11, is used. The lowestpoint occurs next to layer 6, and exposes a part of layer 6 on theridge's side face. FIG. 11 shows the resulting structure after theplasma etching step has been performed. A relatively long over etchingtime has been used, resulting in a relatively large over-etch distanceOE2, as measured from the top of the ridge to the bottom of gap 24. Gap24 is relatively deep, and uncovers sections of both of layers 5 and 9at the side faces. Because the chemical compositions of layers 5 and 9are different, an electrochemical reaction can occur between the layerswhen some types of ionic photo-lithographic solutions become disposedwithin gap 24. The electrochemical reaction causes an undesirableerosion of the ridge. The photo-lithographic solution can be disposed inportion of the crack 21 that extends into gap 24 (FIG. 8), during thephoto-lithographic steps for defining electrodes 1 and 17. In addition,the ionic photo-lithographic solution can etch the exposed portions oflayer 5 and 9 if trapped in gap 24 for a long period of time.

[0059]FIG. 12 shows an embodiment of the novel shaped ridge according tothe present invention after the plasma ashing of resist layer 11.Approximately the same over etching distance OE1 has been used as thatused in the prior art embodiment (FIG. 10). FIG. 13 shows the resultingstructure after the plasma etching step has been performed, where anover-etching distance OE3 is obtained. Although the same over etchingtime has been used as in the prior art case, the value of the OE3 issignificantly less than the over-etch distance OE2, as measured from thetop of the ridge to the bottom of the etched area. In addition, theresulting structure does not have any gaps 24. The reverse mesa slope atthe top section 42 causes the outer side of layer 6 to be etched, ratherthan the inner side. As a result, a relatively smooth transition isformed between the outer side of layer 6 and the side face of layer 9,which significantly reduces the occurrences of cracks 21. After reachingthe etching depth of OE3, further etching of layer 6 is significantlyretarded since the remainder of layer 6 is substantially protected fromthe plasma by layer 9. Accordingly, the novel structure provides arelatively smooth transition surface and tolerates a significant amountover-etching while maintaining the relatively smooth transition surface.In preferred embodiments, the material of layer 9 is more resistant toplasma etching than the material of dielectric layer 6. FIG. 14 showsthe exemplary ridge structure after electrode 7 has been deposited,showing a relatively smooth side surface with no gaps.

[0060] Preferred dimensions of novel ridge structure according to thefirst invention of the present application are now described withreference to FIG. 15, which shows the definitions of the base width A3,the neck width A2, the ridge top width A1, the height H1 from the levelof the base to the level of the neck point, and the height from thelevel of the neck point to the top of the ridge. Ridge top width A1 ispreferably equal to or greater than forty percent (40%) of base widthA3, and preferably less than or equal to sixty-five percent (65%) ofbase width A3. Neck width A2 is preferably greater than or equal toeighty percent (80%) of ridge top width A1 and less than or equal toninety-five percent (95%) of ridge top width A1.

[0061] In one constructed preferred embodiment, A3 has a value of 4 μm,A2 has a value of 1.8 μm, and Al has a value of 2 μm. Height H2 ispreferably between 0.4 μm and 0.6 μm, and more preferably substantiallyequal to 0.5 μm. Height H1 is preferably between 1.3 μm and 1.4 μm.

[0062] It has been mentioned above that the ridge 12 is formed by wetetching. However, the ridge 12 may be formed by dry etching.

[0063] Furthermore, a semiconductor laser device having a simple ridgestripe structure has been taken as an example in the above explanation.However, the present invention may be applied to a semiconductor laserdevice having a double channel structure. In the first case, the ridge12 is formed on top of the substrate's top surface. In the second case,the ridge is formed into the top surface of the substrate by forming oneor more grooves in the substrate at the top surface to define the two ormore sides of the ridge. In this second case, two grooves are generallyused, one on either side of the ridge, but one may use a singlecontinuous groove which encircles the ridge.

[0064] Furthermore, a ridge-type semiconductor laser device has beentaken as an example of semiconductor device in the above explanation.However, the present invention may be applied to, for example, a ridgeguiding semiconductor photodetector.

[0065] Furthermore, a semiconductor laser device has been taken as anexample in the above explanation. However, the present invention can bewidely applied to a general semiconductor device in which a multi-layerfilm is simply formed into a ridge shape by an etching processing.

[0066] As explained above, according to the second invention of thepresent application, the positive electrode (as formed by dry depositionprior to electroplating gold) has thickness of at least 150 nm, and morepreferably of at least 200 nm. Therefore, stress generated on the sideof the ridge is resisted to prevent occurrence of cracks or erosion. Asa result, highly precise semiconductor devices can be obtained with highyield.

[0067] Although the invention has been described with respect to aspecific embodiment for a complete and clear disclosure, the appendedclaims are not to be thus limited but are to be construed as embodyingall modifications and alternative constructions that may occur to oneskilled in the art which fairly fall within the basic teaching hereinset forth.

What is claimed is:
 1. A semiconductor device having a multiple layered ridge, the semiconductor device comprising: an electrode layer that covers at least an upper face of the ridge and at least one side face of the ridge in a longitudinal direction, wherein thickness of said electrode layer on the upper face and the thickness of said electrode layer on the at least one side face of the ridge are substantially same.
 2. The semiconductor device according to claim 1, wherein the thickness of said electrode layer on said at least one side face of said ridge is not smaller than 150 nm.
 3. The semiconductor device according to claim 2, wherein the ridge is supported by a substrate having a top surface and a bottom surface, wherein the ridge is formed at the top surface of the ridge at a first region of the top surface, wherein the top surface of the substrate has a second region located to at least one side of the ridge, and wherein said electrode layer further covers the second region with a thickness that is not smaller than 150 nm.
 4. A method of manufacturing a semiconductor device having a multiple layered ridge, the method comprising the steps of: (a) sequentially forming the multiple layers of the ridge; and (b) forming an electrode layer which covers at least an upper face of the ridge and at least one side face of the ridge in the longitudinal direction in such a manner that the thickness of the electrode layer on the upper face and the thickness of the electrode layer on the at least one side face of the ridge are substantially the same.
 5. The method according to claim 4, wherein the thickness of said electrode layer on the at least one side face of the ridge is not smaller than 150 nm.
 6. The method according to claim 5, wherein the ridge is supported by a substrate having a top surface and a bottom surface, wherein the ridge is formed at the top surface of the ridge at a first region of the top surface, wherein the top surface of the substrate has a second region located to at least one side of the ridge, and wherein the electrode layer further covers the second region with a thickness that is not smaller than 150 nm.
 7. The method according to claim 4, wherein when forming the electrode layer, an electrode forming material is supplied to the at least one side face of the ridge from the upper side.
 8. The method according to claim 4, wherein the ridge is formed at a surface of a substrate, wherein the substrate has a normal vector perpendicular to the surface of the substrate's first surface, wherein step (b) comprises the steps of: (c) exposing the ridge and the substrate to a material deposition process which emits material from a source to the ridge and substrate along a deposition axis with the normal vector of the substrate being inclined at an angle of greater than zero degrees from the deposition direction; (d) during the performance of step (c), rotating the ridge about the normal vector of the substrate.
 9. A semiconductor device comprising: a substrate having a first surface and a second surface; a ridge formed at the first surface of the substrate and comprising at least one layer of a semiconductor material, the ridge having an upper face and at least two side faces; and a conductive layer disposed on at least a portion of the ridge such that the conductive layer covers at least one side face of the ridge with a first thickness (T₁) at said portion, and further covers the ridge's upper face with a second thickness (T₂) at said portion, wherein the first thickness is equal to or greater than fifty percent of the second thickness.
 10. The semiconductor device according to claim 9, wherein the conductive layer comprises one or more sublayers, each sublayer comprising a material which has less than 5% of gold by weight.
 11. The semiconductor device according to claim 9, wherein the conductive layer comprises one or more sublayers, each sublayer comprising a material which has hardness equal to or greater than 30 on the Vickers scale when the material is in its bulk crystalline state.
 12. The semiconductor device according to claim 9, wherein the conductive layer comprises one or more sublayers, each sublayer comprising a material which has a ductility when the material is in its bulk crystalline state which is lower than the ductility of gold.
 13. The semiconductor device according to claim 9, wherein the conductive layer comprises one or more sublayers, each sublayer having a lustrous surface morphology.
 14. The semiconductor device according to claim 9, wherein the ridge is formed on top of the first surface of the substrate.
 15. The semiconductor device according to claim 9, wherein the ridge is formed in the first surface of the substrate with one or more grooves formed in the substrate to define the two or more sides of the ridge.
 16. The semiconductor device according to claim 9, wherein the ridge further comprising a dielectric layer disposed on at least said portion of the ridge and located between the at leas t one side face of the ridge and the conductive layer.
 17. The semiconductor device according to claim 9, wherein said first thickness is greater than or equal to 150 nm.
 18. The semiconductor device according to claim 9, wherein said first thickness is less than or equal to one-hundred and twenty percent of the second thickness.
 19. The semiconductor device according to claim 9, wherein the first thickness is equal to or greater than sixty percent of the second thickness.
 20. The semiconductor device according to claim 19, wherein the first thickness is less than or equal to said second thickness.
 21. The semiconductor device according to claim 9, wherein said first thickness is substantially equal to said second thickness.
 22. A semiconductor device comprising: a substrate having a first surface and a second surface; a ridge formed at the first surface of the substrate and comprising at least one layer of a semiconductor material, the ridge having an upper face and at least two side faces; and a conductive layer disposed on at least a portion of the ridge such that the layer covers at least one side face of the ridge with a first thickness (T₁) at said portion, and further covers the ridge's upper face with a second thickness (T₂) at said portion, wherein said first thickness is greater than or equal to 150 nm.
 23. The semiconductor device according to claim 22, wherein the ridge is formed on top of the first surface of the substrate.
 24. The semiconductor device according to claim 22, wherein the ridge is formed in the first surface of the substrate with one or more grooves formed in the substrate to define the two or more sides of the ridge.
 25. The semiconductor device according to claim 22, wherein the ridge further comprising a dielectric layer disposed on at least said portion of the ridge and located between the at least one side face of the ridge and the conductive layer.
 26. The semiconductor device according to claim 22, wherein said first thickness is greater than or equal to fifty percent of the second thickness and less than or equal to one-hundred and twenty percent of the second thickness.
 27. The semiconductor device according to claim 22, wherein the first thickness is equal to or greater than sixty percent of the second thickness.
 28. The semiconductor device according to claim 27, wherein the first thickness is less than or equal to said second thickness.
 29. The semiconductor device according to claim 22, wherein said first thickness is substantially equal to said second thickness.
 30. The semiconductor device according to claim 22, wherein said first thickness is greater than or equal to 200 nm.
 31. The semiconductor device according to claim 22, wherein the conductive layer material comprises one or more sublayers, each sublayer comprising a material which has less than 5% of gold by weight.
 32. The semiconductor device according to claim 22, wherein the conductive layer comprises one or more sublayers, each sublayer comprising a material which has hardness equal to or greater than 30 on the Vickers scale when the material is in its bulk crystalline state.
 33. The semiconductor device according to claim 22, wherein the conductive layer comprises one or more sublayers, each sublayer comprising a material which has a ductility when the material is in its bulk crystalline state which is lower than the ductility of gold.
 34. The semiconductor device according to claim 22, wherein the conductive layer comprises one or more sublayers, each sublayer having a lustrous surface morphology.
 35. A method of manufacturing a semiconductor device having a multiple layered ridge, the method comprising the steps of: (a) forming a ridge at a first surface of a substrate, the ridge comprising at least one layer of a semiconductor material, and having an upper face and at least two side faces; and (b) forming a conductive layer by dry deposition on at least a portion of the ridge such that the layer covers at least one of the ridge's side face with a first thickness (T₁) at said portion, and further covers the ridge's upper face with a second thickness (T₂) at said portion, wherein the first thickness is equal to or greater than fifty percent of the second thickness, and wherein the conductive layer covers at least a portion of the at least one semiconductor layer.
 36. The method of claim 35 further comprising the steps of: forming a patterned mask on the first surface of the substrate prior to the performance of step (b); stripping the patterned mask with liquid solvent after the performance of step (b) and with the liquid solvent contacting at least a portion of the conductive layer.
 37. The semiconductor device according to claim 35, wherein step (a) comprises the step of forming a dielectric layer on at least said portion of the ridge and located between the at least one side face of the ridge and the conductive layer.
 38. The semiconductor device according to claim 35, wherein the first thickness is greater than or equal to 150 nm.
 39. The semiconductor device according to claim 35, wherein the first thickness is greater than or equal to 200 nm.
 40. The semiconductor device according to claim 35, wherein the first thickness is equal to or greater than fifty percent of the second thickness and is less than or equal to one-hundred and twenty percent of the second thickness.
 41. The semiconductor device according to claim 40, wherein the first thickness is equal to or greater than sixty percent of the second thickness.
 42. The semiconductor device according to claim 41, wherein the first thickness is less than or equal to the second thickness.
 43. The semiconductor device according to claim 35, wherein the first thickness is substantially equal to the second thickness.
 44. The method according to claim 35, wherein the substrate has a normal vector perpendicular to the surface of the substrate's first surface, wherein step (b) comprises the steps of: (c) exposing the ridge and the substrate to a material deposition process which emits material from a source to the ridge and substrate along a deposition axis with the normal vector of the substrate being inclined at an angle of greater than zero degrees from the deposition direction; (d) during the performance of step (c), rotating the ridge about the normal vector of the substrate.
 45. A method of manufacturing a semiconductor device having a multiple layered ridge, the method comprising the steps of: (a) forming a ridge at a first surface of a substrate, the ridge comprising at least one layer of a semiconductor material, and having an upper face and at least two side faces; and (b) forming a conductive layer by dry deposition on at least a portion of the ridge such that the conductive layer covers at least one the ridge's side face with a first thickness (T₁) at said portion, and fu, wherein the first thickness is greater than or equal to 150 nm, and wherrther covers the ridge's upper face with a second thickness (T₂) at said portionein the conductive layer covers at least a portion of the at least one semiconductor layer.
 46. The method of claim 45 further comprising the steps of: forming a patterned mask on the first surface of the substrate prior to the performance of step (b); stripping the patterned mask with liquid solvent after the performance of step (b) and with the liquid solvent contacting at least a portion of the conductive layer.
 47. The semiconductor device according to claim 45, wherein step (a) comprises the step of forming a dielectric layer on at least said portion of the ridge and located between the at least one side face of the ridge and the conductive layer.
 48. The semiconductor device according to claim 45, wherein the first thickness is greater than or equal to 200 nm.
 49. The semiconductor device according to claim 45, wherein the first thickness is equal to or greater than fifty percent of the second thickness and is less than or equal to one-hundred and twenty percent of the second thickness.
 50. The method according to claim 45, wherein the substrate has a normal vector perpendicular to the surface of the substrate's first surface, wherein step (b) comprises the steps of: (c) exposing the ridge and the substrate to a material deposition process which emits material from a source to the ridge and substrate along a deposition axis with the normal vector of the substrate being inclined at an angle of greater than zero degrees from the deposition direction; (d) during the performance of step (c), rotating the ridge about the normal vector of the substrate.
 51. A semiconductor device comprising: a substrate having a top surface and a bottom surface; a ridge formed at the top surface of the substrate and comprising at least one layer of a semiconductor material, the ridge having a base attached to the substrate, an upper face located above the base, a first body section located between the base and the upper face, a second body section located between the first body section and the upper face, and at least a first side face located between the ridge's upper face and the base and located to one side of the first and second body sections, the first side face having a first area which spans over the first body section and a second area which spans over the second body section, the first side face further having a straight mesa slope or a forward mesa slope in the first area and a reverse mesa slope in the second area; and a dielectric layer disposed on the first side face and covering the first area and at least a portion of the second area which is closest to the first area.
 52. The semiconductor device of claim 51 wherein the dielectric layer is disposed to cover the entire first and second areas.
 53. The semiconductor device of claim 51 wherein the top surface portion of the ridge comprises a material which is more resistance to plasma etching than the material of the dielectric layer.
 54. The semiconductor device of claim 51 further comprising a layer of conductive material disposed over the dielectric layer, the upper face of the ridge, and a portion of the second area of the first side face which is closest to the upper face of the ridge.
 55. The semiconductor device of claim 51 wherein the ridge has a base width (A3) along the cross-sectional width of the base, the base width having a value in a range of 2.7 μm to 4.5 μm; wherein the ridge has a top width (A1) along the cross-sectional width of the ridge's top face, the top width having a value in the range of forty percent of the base width to sixty-five percent of the base width; wherein the ridge has an interface plane between the first and second body sections of the ridge, wherein the ridge has a neck width (A2) along the cross-sectional width of the ridge at the interface plane, and wherein the neck width has a value in the range of eighty percent of the ridge top width to ninety-five percent of the ridge top width.
 56. The semiconductor device of claim 55 wherein the ridge has a first height (H1) from the base to the interface plane and a second height (H2) from the interface plane to the top surface of the ridge, wherein the first height has a value in the range of 1.3 μm to 1.4 μm, and wherein the second height has a value in the range of 0.4 μm to 0.6 μm.
 57. The semiconductor device of claim 51 further comprising a conductive layer disposed over a portion of the first side face at a first thickness (T₁) and an adjacent portion of the upper face of the ridge at a second thickness (T₂), said first thickness being equal to or greater than fifty percent of the second thickness, said conductive layer comprises one or more sublayers, each sublayer comprising a material which has less than 5% of gold by weight.
 58. The semiconductor device of claim 57 wherein said first thickness is greater than or equal to 150 nm.
 59. The semiconductor device of claim 57 wherein the first thickness is less than or equal to one-hundred and twenty percent of the second thickness.
 60. The semiconductor device according to claim 57, wherein the first thickness is equal to or greater than sixty percent of the second thickness.
 61. The semiconductor device according to claim 60, wherein the first thickness is less than or equal to said second thickness.
 62. The semiconductor device according to claim 57, wherein said first thickness is substantially equal to said second thickness.
 63. The semiconductor device of claim 51 further comprising a conductive layer disposed over a portion of the first side face at a first thickness (T₁) and an adjacent portion of the upper face of the ridge at a second thickness (T₂), said first thickness is greater than or equal to 150 nm, said conductive layer comprises one or more sublayers, each sublayer comprising a material which has less than 5% of gold by weight. 